Code |
Name of the Course Unit |
Semester |
In-Class Hours (T+P) |
Credit |
ECTS Credit |
EEE209 |
LOGICAL CIRCUIT DESIGN |
5 |
4 |
3 |
5 |
GENERAL INFORMATION |
Language of Instruction : |
İngilizce |
Level of the Course Unit : |
LİSANS, TYY: + 6.Düzey, EQF-LLL: 6.Düzey, QF-EHEA: 1.Düzey |
Type of the Course : |
Zorunlu |
Mode of Delivery of the Course Unit |
- |
Coordinator of the Course Unit |
Dr.Öğr.Üyesi OĞUZHAN ÖZTAŞ |
Instructor(s) of the Course Unit |
|
Course Prerequisite |
No |
OBJECTIVES AND CONTENTS |
Objectives of the Course Unit: |
To introduce students into the world of digital design.
To discuss all aspects of design and implementation methods.
To give an understanding of the design issues in combinational logic circuits.
To give an understanding of the design issues in sequential logic circuits. |
Contents of the Course Unit: |
To introduce students into the world of digital design.
To discuss all aspects of design and implementation methods.
To give an understanding of the design issues in combinational logic circuits.
To give an understanding of the design issues in sequential logic circuits. |
KEY LEARNING OUTCOMES OF THE COURSE UNIT (On successful completion of this course unit, students/learners will or will be able to) |
LO-1 Carry out arithmetic operations by using 2's complement representation of binary numbers.
LO-2 Employ Boolean Algebra in logic circuits modelling.
LO-3 Analyse Combinational Logic Circuits which include Small, Medium or Large Scale Integrated components, by using various methods.
LO-4 Design Combinational Logic Circuits which include Small, Medium or Large Scale Integrated components, by using various methods.
LO-5 Analyse Synchronous Sequential Logic Circuits which include Small, Medium or Large Scale Integrated components, by using various methods.
LO-6 Design Synchronous Sequential Logic Circuits which include Small, Medium or Large Scale Integrated components, by using various methods.
LO-7 Analyse/synthesize sequential logic circuits which include registers and counters (medium scale integrated components), by using various methods.
LO-8 Analyse/synthesize sequential logic circuits which include programmable logic arrays (large scale integrated components), by using various methods. |
WEEKLY COURSE CONTENTS AND STUDY MATERIALS FOR PRELIMINARY & FURTHER STUDY |
Week |
Preparatory |
Topics(Subjects) |
Method |
1 |
- |
Introduction to the course, Binary Numbers, Number Base Conversion, Complements, Signed Numbers, Binary Codes |
- |
2 |
- |
Introduction to Boolean Algebra, Theorems & Properties of Boolean Algebra, Boolean Functions, Canonical and Standard Forms |
- |
3 |
- |
Other Logic Operations, K-Maps, Simplification of Boolean Functions, Product of Sums Simplifications |
- |
4 |
- |
Don’t-Care Conditions, NAND and NOR Implementations, Exclusive-OR, Analysis of Combinational Circuits |
- |
5 |
- |
Design of Combinational Circuits, Binary Adders, Decimal Adders, Binary Multipliers, Magnitude Comparators |
- |
6 |
- |
Decoders, Demultiplexers, Encoders, Multiplexers |
- |
7 |
- |
Introduction to Sequential Logic, Latches, Flip-Flops |
- |
8 |
- |
ARA SINAV |
- |
9 |
- |
Analysis of Sequential Circuits |
- |
10 |
- |
Design of Sequential Circuits, Advanced topics in sequential circuit design |
- |
11 |
- |
Registers and Counters |
- |
12 |
- |
Registers and Counters |
- |
13 |
- |
Memory and Programmable Logic |
- |
14 |
- |
Memory and Programmable Logic |
- |
15 |
- |
Review |
- |
16 |
- |
FİNAL |
- |
17 |
- |
FİNAL |
- |
SOURCE MATERIALS & RECOMMENDED READING |
"Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog", Sixth Edition, Mano and Ciletti, Pearson, 2018. |
ASSESSMENT |
Assessment & Grading of In-Term Activities |
Number of Activities |
Degree of Contribution (%) |
Description |
Level of Contribution |
0 |
1 |
2 |
3 |
4 |
5 |
CONTRIBUTION OF THE COURSE UNIT TO THE PROGRAMME LEARNING OUTCOMES
KNOWLEDGE |
Theoretical |
|
Programme Learning Outcomes |
Level of Contribution |
0 |
1 |
2 |
3 |
4 |
5 |
1 |
Explains the fundamental engineering concepts of computer science and relates them to the groundwork of computer science.
|
|
|
|
|
|
|
KNOWLEDGE |
Factual |
|
Programme Learning Outcomes |
Level of Contribution |
0 |
1 |
2 |
3 |
4 |
5 |
1 |
Uses theoretical and practical knowledge coming from mathematics, probability, statistics and various other branches of life sciences, to find solutions to engineering problems.
|
|
|
|
|
|
|
SKILLS |
Cognitive |
|
Programme Learning Outcomes |
Level of Contribution |
0 |
1 |
2 |
3 |
4 |
5 |
1 |
Determines the components and the underlying process of a system and designs an appropriate computational model under reasonable constraints.
|
|
|
|
|
|
|
2 |
Designs a computer-aided conceptual model with modern techniques.
|
|
|
|
|
|
|
SKILLS |
Practical |
|
Programme Learning Outcomes |
Level of Contribution |
0 |
1 |
2 |
3 |
4 |
5 |
1 |
Determines, detects and analyzes the areas of computer science applications and develops appropriate solutions.
|
|
|
|
|
|
|
2 |
Identifies, models and solves computer engineering problems by applying appropriate analytical methods.
|
|
|
|
|
|
|
3 |
Determines and uses the necessary information technologies in an efficient way for engineering applications.
|
|
|
|
|
|
|
OCCUPATIONAL |
Autonomy & Responsibility |
|
Programme Learning Outcomes |
Level of Contribution |
0 |
1 |
2 |
3 |
4 |
5 |
1 |
Possess the responsibility and ability to design and conduct experiments for engineering problems by collecting, analyzing and interpreting data.
|
|
|
|
|
|
|
2 |
Possess the ability to conduct effective individual study.
|
|
|
|
|
|
|
3 |
Takes responsibility as a team work and contributes in an effective way.
|
|
|
|
|
|
|
WORKLOAD & ECTS CREDITS OF THE COURSE UNIT |
Workload for Learning & Teaching Activities |
Type of the Learning Activites |
Learning Activities (# of week) |
Duration (hours, h) |
Workload (h) |
Ders |
14 |
4 |
56 |
Derse Ön Hazırlık ve Ders Sonrası Pekiştirme |
1 |
2 |
2 |
Arazi Çalışması |
0 |
0 |
0 |
Grup Çalışması / Ödevi |
2 |
5 |
10 |
Laboratuvar |
2 |
2 |
4 |
Okuma |
0 |
0 |
0 |
Ödev |
2 |
5 |
10 |
Proje Hazırlama |
2 |
6 |
12 |
Seminer |
0 |
0 |
0 |
Staj |
0 |
0 |
0 |
Teknik Gezi |
1 |
1 |
1 |
Web Tab. Öğrenme |
0 |
0 |
0 |
Uygulama |
3 |
4 |
12 |
Yerinde Uygulama |
1 |
2 |
2 |
Mesleki Faaliyet |
1 |
2 |
2 |
Sosyal Faaliyet |
0 |
0 |
0 |
Tez Hazırlama |
0 |
0 |
0 |
Alan Çalışması |
0 |
0 |
0 |
Rapor Yazma |
2 |
5 |
10 |
Final Sınavı |
1 |
1 |
1 |
Final Sınavı Hazırlığı |
1 |
1 |
1 |
Ara Sınav |
1 |
1 |
1 |
Ara Sınav Hazırlığı |
1 |
1 |
1 |
Kısa Sınav |
1 |
1 |
1 |
Kısa Sınav Hazırlığı |
1 |
1 |
1 |
TOPLAM |
37 |
0 |
127 |
|
Total Workload of the Course Unit |
127 |
|
|
Workload (h) / 25.5 |
5 |
|
|
ECTS Credits allocated for the Course Unit |
5,0 |
|